Cerebras is interesting because it approaches the AI inference problem from the opposite direction to most accelerator designers. Instead of connecting thousands of ordinary-sized chips and accepting the cost of moving data between them, it uses almost an entire silicon wafer as one processor.
The current WSE-3 Turbo has 900,000 cores and 44 GB of SRAM on the wafer. The point isn't just raw FLOPS. It's that decoding a language model often spends much of its time moving model weights and intermediate data. If memory and computation are tightly integrated, there is less movement and less latency.
Cerebras has published extremely high token-generation speeds. Its new CS-4 system uses three wafer-scale engines, and company tests show more than 4,400 output tokens per second per user on GPT-OSS-120B. That number needs the usual caveat: performance changes with model, sequence length, batching and system configuration. It doesn't mean every application runs 30 times faster than on a GPU.
But a narrow speed advantage could have broad consequences. Consider an agent that makes twenty sequential model calls while editing code, checking a result and trying again. Even if each call is useful, those latencies accumulate. An assistant that completes a task in thirty seconds rather than several minutes is a different product. It can become part of an interactive workflow instead of something you start and periodically check.
There's a second reason to watch the architecture: inference may increasingly be split between prefill and decode. Prefill, which processes the prompt, is compute intensive. Decode, which produces the response, can be limited by memory bandwidth. It isn't obvious that the best hardware for one stage is also the best for the other. AWS and AMD have both announced work with Cerebras around these heterogeneous systems. Oracle plans to offer Cerebras inference in its cloud during 2027.
The roadmap gets more interesting. CS-5 is targeting much higher per-user speeds in 2027. The planned CS-6 is supposed to combine wafer-scale SRAM and compute with 3D-stacked DRAM. That could increase the amount of model state held close to the processors, reducing the number of systems and links required for very large models. This is a plan, not yet a proven product, and manufacturing a stacked wafer-scale system won't be simple.
The obvious objection is competition. Nvidia still has a tremendous software advantage. Google and Amazon have their own silicon. OpenAI has developed Jalapeño with Broadcom, while Groq and SambaNova offer other inference architectures. Nor does the fastest single-user decode necessarily mean the best cost per token at high utilization.
There's also a real question about hardware durability. A recent short report alleged unusually short wafer lifetimes; Cerebras disputes the claim and points to its operating history and qualification data. We need more years of field evidence before that is settled.
What seems increasingly likely, though, is that future data centers will use several kinds of AI accelerators rather than one chip for every workload. The interesting question isn't whether wafer-scale replaces GPUs. It's how large the market becomes for a processor optimized for extremely low-latency generation.
For people deploying LLM systems: would you pay a premium for much faster per-user decoding, or is aggregate throughput per watt still the metric that dominates your decisions?
Position: 200 shares bought at $99.3